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22504 tn im sk no.7773-1/22 ver.1.02 o1502 preliminary overview the lc8774c8b, LC8774B2B, lc877496b and lc877480b are 8 bit single chip microcontrollers with the following on-chip functional blocks: ? cpu: operable at a minimum bus cycle time of 100ns ? on-chip rom maximum capacity: lc8774c8b 128k bytes LC8774B2B 112k bytes lc877496b 96k bytes lc877480b 80k bytes ? on-chip ram capacity: 4096 bytes ? lcd controller / driver ? 16 bit timer / counter (can be divided into 8 bit timer) ? 16 bit timer (can be divided into 8 bit timer, 8 bit timer can be pwm) ? four 8 bit timer with prescalers ? timer for use as date / time clock ? synchronous serial i/o port (with automatic block transmit / receive function) ? asynchronous / synchronous serial i/o port ? 15 channel 8 bit ad converter ? small signal detector ? high-speed clock counter ? system clock divider ? 20 source 10 vectored interrupt system ordering number : enn*7773 8 bit single chip microcontroller incorporating 128k/112k/96k/80k byte rom and 4096 byte ram on chip lc8774c8b/b2b/96b/80b cmos ic package dimensions unit: mm 3151a [ lc8774c8b/b2b/96b/80b ] ? unit: mm 3274 [ lc8774c8b/b2b/96b/80b ]
lc8774c8b/b2b/96b/80b no.7773-2/22 features (1) read-only memory (rom) ? 49152 8 bits (lc877148a) ? 40960 8 bits (lc877140a) ? 32768 8 bits (lc877132a) ? 24576 8 bits (lc877124a) (2) random access memory (ram): 4096 9 bits (lc8774c8b, lc 8774b2b, lc877496b , lc877480b) (3) minimum bus cycle time: 100 ns (10mhz) note: the bus cycle time indicates rom read time. (4) minimum instruction cycle time: 300 ns (10mhz) (5) ports ? input / output ports data direction programmable for each bit individually: 26 (p1n, p30 to p35, p70 to p73, p8n) data direction programmable in nibble units: 8 (p0n) (when n-channel open drain output is selected, data can be input in bit units.) ? input ports: 2 (xt1, xt2) ? lcd ports segment output: 48 (s00 to s47) common output: 4 (com0 to com3) bias terminals for lcd driver: 3 (v1 to v3) other functions input / output ports: 48 (pan, pbn, pcn, pdn, pen, pfn) input ports: 7 (pln) ? oscillator pins: 2 (cf1, cf2) ? reset pin: 1 ( res ) ? power supply: 6 (v ss 1 to 3, v dd 1 to 3) (6) lcd controller ? seven display modes are available (static, 1/2, 1/3, 1/4 duty 1/2, 1/3 bias) ? segment output and common output can be switc hed to general purpose input / output ports. (7) small signal detection (mic signals etc) ? counts pulses with the level which is greater than a preset value ? 2 bit counter (8) timers ? timer 0: 16 bit timer / counter with capture register mode 0: 2 channel 8 bit timer with programmable 8 bit prescaler and 8 bit capture register mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8 bit capture register mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register mode 3: 16 bit counter with 16 bit capture register ? timer 1: pwm / 16 bit timer / counter with toggle output function mode 0: 8 bit timer (with toggle output) + 8 bit timer / counter (with toggle output) mode 1: 2 channel 8 bit pwm mode 2: 16 bit timer / counter (with toggle output) toggle output from lower 8 bits is also possible. mode 3: 16 bit timer (with toggle output) lower order 8 bits can be used as pwm. ? timer 4: 8 bit timer with 6 bit prescaler ? timer 5: 8 bit timer with 6 bit prescaler ? timer 6: 8 bit timer with 6 bit prescaler ? timer 7: 8 bit timer with 6 bit prescaler continued on next page.
lc8774c8b/b2b/96b/80b no.7773-3/22 continued from preceding page. ? base timer 1) the clock signal can be sel ected from any of the following: sub-clock (32.768khz crystal oscillator), system clock, and prescaler output from timer 0 2) interrupts of five different time intervals are possible. (9) high-speed clock counter ? countable up to 20mhz clock (when using 10mhz main clock) ? real time output (10) serial-interface ? sio 0: 8 bit synchronous serial interface 1) lsb first / msb first is selectable 2) internal 8 bit baud-rate genera tor (fastest clock period 4 / 3 tcyc) 3) consecutive automatic data communication (1 to 256 bits) ? sio 1: 8 bit asynchronous / synchronous serial interface mode 0: synchronous 8 bit serial i o (2-wire or 3-wire, transmit clock 2 to 512 tcyc) mode 1: asynchronous serial i o (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tcyc) mode 2: bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tcyc) mode 3: bus mode 2 (start detection, 8 data bits, stop detection) (11) ad converter ? 8 bits 15 channels (12) remote control receiver circuit (conn ected to p73 / int3 / t0in terminal) ? noise rejection function (noise re jection filter?s time constant can be selected from 1 / 32 / 128 tcyc) (13) watchdog timer ? the watching time period is determined by an external rc. ? watchdog timer can produce interrupt or system reset (14) interrupts: 20 sources, 10 vectors 1) three priority (low, high and highe st) multiple interrupts are supported. during interrupt handling, an equal or lowe r priority interrupt request is postponed. 2) if interrupt requests to two or more vector addresses occur at once, the hi gher priority interrupt takes precedence. in the case of equal priority levels, the vect or with the lowest address takes precedence. no. vector selectable level interrupt signal 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2 / t0l / int4 4 0001bh h or l int3 / base timer / int5 5 00023h h or l t0h 6 0002bh h or l t1l / t1h 7 00033h h or l sio0 8 0003bh h or l sio1 9 00043h h or l adc / mic / t6 / t7 10 0004bh h or l port 0 / t4 / t5 ? priority level: x > h > l ? for equal priority levels, vector with lowest address takes precedence. (15) subroutine stack levels: 2048 levels max. stack is located in ram. (16) multiplication and division ? 16 bit 8 bit (executed in 5 cycles) ? 24 bit 16 bit (12 cycles) ? 16 bit 8 bit (8 cycles) ? 24 bit 16 bit (12 cycles)
lc8774c8b/b2b/96b/80b no.7773-4/22 (17) oscillation circuits ? on-chip rc oscillation for system clock use. ? cf oscillation for system clock use. (rf built in, rd external) ? crystal oscillation low speed system clock use. (rf built in, rd external) ? on-chip frequency variable rc oscillation circuit for system clock use. (18) system clock divider ? low power consumption operation is available ? minimum instruction cycle time (300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, 76.8 s can be switched by program (when using 10mhz main clock) (19) standby function ? halt mode halt mode is used to reduce power consumption. during the halt mode, program execution is stopped but peripheral circuits keep operating (some pa rts of serial transfer operation stop.) 1) oscillation circuits ar e not stopped automatically. 2) released by the system reset or interrupts. ? hold mode hold mode is used to reduce power consumption. pr ogram execution and peripheral circuits are stopped. 1) cf, rc and crystal oscillation circuits stop automatically. 2) released by any of the following conditions. (1) low level input to the reset pin (2) specified level input to one of int0, int1, int2, int4, int5 (3) port 0 interrupt ? x?tal hold mode x?tal hold mode is used to reduce power consumption. program execution is stopped. all peripheral circuits except the base timer are stopped. 1) cf and rc oscillation circuits stop automatically. 2) crystal oscillator operation is kept in its state at hold mode inception. 3) released by any of the following conditions. (1) low level input to the reset pin (2) specified level input to one of int0, int1, int2, int4, int5 (3) port 0 interrupt (4) base-timer interrupt (20) package ? qip100e [ lead free product ] ? tqfp100 [ lead free product ] (21) development tools ? evaluation chip: lc876093 ? emulator: eva62s + ecb876600 (evaluation chip board) + sub877400 + pod100qfp or pod100sqfp (type b) : ice-b877300 + sub877400 + pod100qfp or pod100sqfp (type b) ? flash rom version: lc87f74c8a
lc8774c8b/b2b/96b/80b no.7773-5/22 pin assignment s20/pc4 s19/pc3 s18/pc2 s17/pc1 s16/pc0 s15/pb7 s14/pb6 s13/pb5 s12/pb4 s11/pb3 s10/pb2 s9/pb1 s8/pb0 s7/pa7 s6/pa6 s5/pa5 s4/pa4 s3/pa3 s2/pa2 s1pa1 v2/pl5/an13 v1/pl4/an12 com0/pl0 com1/pl1 com2/pl2 com3/pl3 p30/int4/t1in p31/int4/t1in v ss 3 v dd 3 p32/int4/t1in p33/int4/t1in p34/int5/t1in p35/int5/t1in p00 p01 p02 p03 p04 p05 p06 p07 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7/micin p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in p73/int3/t0in s0/pa0 v3/pl6/an14 s47/pf7 s46/pf6 s45/pf5 s44/pf4 s43/pf3 s42/pf2 s41/pf1 s40/pf0 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 v ss 2 v dd 2 s23/pc7 s22/pc6 s21/pc5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 lc8774c8b LC8774B2B lc877496b lc877480b top view sanyo : qip100e [ lead free product ]
lc8774c8b/b2b/96b/80b no.7773-6/22 pin assignment s47/pf7 v3/pl6/an14 v2/pl5/an13 v1/pl4/an12 com0/pl0 com1/pl1 com2/pl2 com3/pl3 p30/int4/t1in p31/int4/t1in v ss 3 v dd 3 p32/int4/t1in p33/int4/t1in p34/int5/t1in p35/int5/t1in p00 p01 p02 p03 p04 p05 p06 p07 p10/so0 s23/pc7 s22/pc6 s21/pc5 s20/pc4 s19/pc3 s18/pc2 s17/pc1 s16/pc0 s15/pb7 s14/pb6 s13/pb5 s12/pb4 s11/pb3 s10/pb2 s9/pb1 s8/pb0 s7/pa7 s6/pa6 s5/pa5 s4/pa4 s3/pa3 s2/pa2 s1pa1 s0/pa0 p73/int3/t0in p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7/micin p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in s46/pf6 s45/pf5 s44/pf4 s43/pf3 s42/pf2 s41/pf1 s40/pf0 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 v ss 2 v dd 2 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 lc8774c8b LC8774B2B lc877496b lc877480b top view sanyo : tqfp100 [ lead free product ]
lc8774c8b/b2b/96b/80b no.7773-7/22 system block diagram interrupt control stand-by control ir pla rom pc bus interface port 0 port 1 sio0 sio1 base timer lcd controller int0 to 5 noise rejection filter port 3 port 7 port 8 adc small signal detector acc b register c register psw rar ram stack pointer watchdog timer alu timer 4 timer 5 timer 6 timer 7 timer 0 (high-speed clock counter) timer 1 clock generator cf rc mrc x?tal
lc8774c8b/b2b/96b/80b no.7773-8/22 pin description pin name i/o function option v ss 1, v ss 2, v ss 3 - ? power supply (-) no v dd 1, v dd 2, v dd 3 - ? power supply (+) no port 0 p00 to p07 i/o ? 8 bit input / output port ? data direction programmable in nibble units ? use of pull-up resistor can be specified in nibble units ? input for hold release ? input for port 0 interrupt yes port 1 p10 to p17 i/o ? 8 bit input / output port ? data direction programmable for each bit ? use of pull-up resistor can be s pecified for each bit individually ? other pin functions p10: sio0 data output p11: sio0 data input or bus input / output p12: sio0 clock input / output p13: sio1 data output p14: sio1 data input or bus input / output p15: sio1 clock input / output p16: timer 1 pwml output p17: timer 1 pwmh output / buzzer output yes port 3 p30 to p35 i/o ? 6 bit input / output port ? data direction can be specified for each bit ? use of pull-up resistor can be s pecified for each bit individually ? other functions p30 to p33: int4 input / hold re lease input / timer 1 event input / timer 0l capture input / timer 0h capture input p34 to p35: int5 input / hold re lease input / timer 1 event input / timer 0l capture input / timer 0h capture input ? interrupt detection selection rising falling rising and falling h level l level int4 int5 yes yes yes yes yes yes no no no no yes port 7 p70 to p73 i/o ? 4 bit input / output port ? data direction can be specified for each bit ? use of pull-up resistor can be s pecified for each bit individually ? other functions p70: int0 input / hold release input / timer 0l capture input / output for watchdog timer p71: int1 input / hold release input / timer 0h capture input p72: int2 input / hold release input / ti mer 0 event input / timer 0l capture input p73: int3 input (noise rejection filter a ttached) / timer 0 event input / timer 0h capture input ad input port: an8 (p70), an9 (p71) ? interrupt detection selection rising falling rising and falling h level l level int0 int1 int2 int3 yes yes yes yes yes yes yes yes no no yes yes yes yes no no yes yes no no no port 8 p80 to p87 i/o ? 8 bit input / output port ? input / output can be specified for each bit individually ? other functions: ad input ports: an0 to an7 small signal detector input port: micin (p87) no continued on next page.
lc8774c8b/b2b/96b/80b no.7773-9/22 continued from preceding page. pin name i/o function option s0 / pa0 to s7 / pa7 i/o ? segment output for lcd ? can be used as general purpos e input / output port (pa) no s8 / pb0 to s15 / pb7 i/o ? segment output for lcd ? can be used as general purpos e input / output port (pb) no s16 / pc0 to s23 / pc7 i/o ? segment output for lcd ? can be used as general purpos e input / output port (pc) no s24 / pd0 to s31 / pd7 i/o ? segment output for lcd ? can be used as general purpos e input / output port (pd) no s32 / pe0 to s39 / pe7 i/o ? segment output for lcd ? can be used as general purpos e input / output port (pe) no s40 / pf0 to s47 / pf7 i/o ? segment output for lcd ? can be used as general purpos e input / output port (pf) no com0 / pl0 to com3 / pl3 i/o ? common output for lcd ? can be used as general purpose input port (pl) no v1 / pl4 to v3 / pl6 i/o ? lcd output bias power supply ? can be used as general purpose input port (pl) ? other functions: ad input ports: an12 to an14 no res i reset terminal no xt1 i ? input for 32.768khz crystal oscillation ? other functions: general purpose input port ad input port: an10 ? when not in use, connect to v dd 1 no xt2 i/o ? output for 32.768khz crystal oscillation ? other functions: general purpose input port ad input port: an11 ? when not in use, set to oscillation mode and leave open no cf1 i input terminal fo r ceramic oscillator no cf2 o output terminal fo r ceramic oscillator no port configuration port form and pull-up resistor options are shown in the following table. port status can be read even when port is set to output mode. terminal option applies to: options output form pull-up resistor 1 cmos programmable (note 1) p00 to p07 each bit 2 nch-open drain none 1 cmos programmable p10 to p17 each bit 2 nch-open drain programmable 1 cmos programmable p30 to p35 each bit 2 nch-open drain none p70 - none nch-open drain programmable p71 to p73 - none cmos programmable p80 to p87 - none nch-open drain none s0 / pa0 to s47 / pf7 - none cmos programmable com0 / pl0 to com3 / pl3 - none input only none v1 / pl4 to v3 / pl6 - none input only none xt1 - none input only none xt2 - none output for 32.768k hz crystal oscillation none note 1 attachment of port 0 programmable pull-up resistors is controllable in nibble units (p00 to 03, p04 to 07).
lc8774c8b/b2b/96b/80b no.7773-10/22 *note 1: connect as follows to reduce noise on v dd . v ss 1, v ss 2 and v ss 3 must be connected together and grounded. *note 2: the power supply for the internal memory is v dd 1 but it uses the v dd 3 as the power supply for ports. when the v dd 3 is not backed up, the port level does not become ?h? even if the port latch is in the ?h? level. therefore, when the v dd 3 is not backed up and the port latch is ?h? level, the port level is unstable in the hold mode, and the back up time becomes shor ter because the through current runs from v dd to gnd in the input buffer. if v dd 3 is not backed up, output ?l? by the program or pull the port to ?l? by the external circuit in the hold mode so that the port level becomes ?l? level and unnecessary current consumption is prevented. absolute maximum ratings / ta=25 c, v ss 1=v ss 2=v ss 3=0v parameter symbol pins conditions v dd [v] min typ max unit supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1=v dd 2=v dd 3 -0.3 +7.0 supply voltage for lcd vlcd v1 / pl4, v2 / pl5, v3 / pl6 v dd 1=v dd 2=v dd 3 -0.3 v dd input voltage v i port l xt1, xt2, cf1, res -0.3 v dd +0.3 input / output voltage v io 1 ?port 0, 1, 3, 7, 8 ?port a, b, c, d, e, f -0.3 v dd +0.3 v [high level output current] ioph1 port 0, 1, 3 ?cmos output selected ?current at each pin -10 ioph2 port 71, 72, 73 current at each pin -3 peak output current ioph3 port a, b, c, d, e, f current at each pin -5 ioah1 port 0, 1, 32, 33, 34, 35 total of all pins -40 ioah2 port 30, 31 total of all pins -10 ioah3 port 7 total of all pins -5 ioah4 port a, b, c total of all pins -25 total output current ioah5 port d, e, f total of all pins -25 ma [low level output current] iopl1 port 0, 1, 32 to 35 current at each pin 20 iopl2 port 30, 31 current at each pin 30 iopl3 port 7, 8 current at each pin 5 peak output current iopl4 port a, b, c, d, e, f current at each pin 15 ioal1 port 0, 1, 32, 33, 34, 35 total of all pins 60 ioal2 port 30, 31 total of all pins 60 ioal3 port 7, 8 total of all pins 20 ioal4 port a, b, c total of all pins 40 total output current ioal5 port d, e, f total of all pins 40 ma qip100e 517 maximum power consumption pd max tqfp100 ta = -30 to +70 c 388 mw operating temperature range topr -30 +70 storage temperature range tstg -55 +125 c lsi v dd 1 back-up capacitors *2 v dd 2 v dd 3 v ss 2 v ss 1 p owe r supply v ss 3
lc8774c8b/b2b/96b/80b no.7773-11/22 recommended operating range / ta=-30 c to +70 c, v ss 1=v ss 2=v ss 3=0v parameter symbol pins conditions v dd [v] min typ max unit v dd 1 0.294 s tcyc 200 s 4.5 6.0 operating supply voltage range v dd 2 v dd 1=v dd 2=v dd 3 0.735 s tcyc 200 s 2.5 6.0 supply voltage range in hold mode vhd v dd 1 keep ram and register data in hold mode 2.0 6.0 v ih 1 ?port 0, 3, 8 ?port a, b, c, d, e, f, l output disable 2.5 to 6.0 0.3v dd +0.7 v dd v ih 2 ?port 1 ?port 71, 72, 73 ?p70 port input / interrupt output disable 2.5 to 6.0 0.3v dd +0.7 v dd v ih 3 port 87 small signal input output disable 2.5 to 6.0 0.75v d d v dd v ih 4 port 70 watchdog timer output disable 2.5 to 6.0 0.9v dd v dd input high voltage v ih 5 xt1, xt2, cf1, res 2.5 to 6.0 0.75v d d v dd v il 1 ?port 0, 3, 8 ?port a, b, c, d, e, f, l output disable 2.5 to 6.0 v ss 0.15v d d +0.4 v il 2 ?port 1 ?port 71, 72, 73 ?p70 port input / interrupt output disable 2.5 to 6.0 v ss 0.1v dd +0.4 v il 3 port 87 small signal input output disable 2.5 to 6.0 v ss 0.25v d d v il 4 port 70 watchdog timer output disable 2.5 to 6.0 v ss 0.8v dd -1.0 input low voltage v il 5 xt1, xt2, cf1, res 2.5 to 6.0 v ss 0.25v d d v 4.5 to 6.0 0.294 200 operation cycle time tcyc 2.5 to 6.0 0.735 200 s 4.5 to 6.0 0.1 10 ?cf2 open ?system clock divider : 1/1 ?external clock duty = 50 5% 2.5 to 6.0 0.1 4 4.5 to 6.0 0.2 20 external system clock frequency fexcf1 cf1 ?cf2 open ?system clock divider : 1/2 2.5 to 6.0 0.2 8 fmcf1 cf1, cf2 10mhz ceramic resonator oscillation refer to figure 1 4.5 to 6.0 10 fmcf2 cf1, cf2 4mhz ceramic resonator oscillation refer to figure 1 2.5 to 6.0 4 fmrc rc oscillation 2.5 to 6.0 0.3 1.0 2.0 fmmrc frequency variable rc oscillation source oscillation 2.5 to 6.0 50 mhz oscillation frequency range (note 1) fsx?tal xt1, xt2 32.768khz crystal resonator oscillation refer to figure 2 2.5 to 6.0 32.768 khz (note 1) the port value of oscillation circuit is shown in table 1 and table 2.
lc8774c8b/b2b/96b/80b no.7773-12/22 electrical characteristics / ta=-30 c to +70 c, v ss 1=v ss 2=v ss 3=0v parameter symbol pins conditions v dd [v] min typ max unit i ih 1 ?port 0, 1, 3, 7, 8 ?port a, b, c, d, e, f, l ?output disabled ?pull-up resister off ?v in =v dd (including off state leak current of the output tr.) 2.5 to 6.0 1 i ih 2 res v in =v dd 2.5 to 6.0 1 i ih 3 xt1, xt2 when configured as an input port v in =v dd 2.5 to 6.0 1 i ih 4 cf1 v in =v dd 2.5 to 6.0 15 high level input current i ih 5 p87 / an7 / micin small signal input v in =vbis + 0.5v (vbis : bias voltage) 2.5 to 6.0 4.2 8.5 15 i il 1 ?port 0, 1, 3, 7, 8 ?port a, b, c, d, e, f, l ?output disabled ?pull-up resister off ?v in =v ss (including off state leak current of the output tr.) 2.5 to 6.0 -1 i il 2 res v in =v ss 2.5 to 6.0 -1 i il 3 xt1, xt2 when configured as an input port v in =v ss 2.5 to 6.0 -1 i il 4 cf1 v in =v ss 2.5 to 6.0 -15 low level input current i il 5 p87 / an7 / micin small signal input v in =vbis - 0.5v (vbis : bias voltage) 2.5 to 6.0 -15 -8.5 -4.2 a v oh 1 i oh =-1.0ma 4.5 to 6.0 v dd -1 v oh 2 port 0, 1, 3 : cmos output option i oh =-0.1ma 2.5 to 6.0 v dd -0.5 v oh 3 port 7 i oh =-0.4ma 2.5 to 6.0 v dd -1 v oh 4 i oh =-1.0ma 4.5 to 6.0 v dd -1 high level output voltage v oh 5 port a, b, c, d, e, f i oh =-0.1ma 2.5 to 6.0 v dd -0.5 v ol 1 i ol =10ma 4.5 to 6.0 1.5 v ol 2 port 0, 1, 3 i ol =1.6ma 2.5 to 6.0 0.4 v ol 3 port 30, 31 i ol =30ma 4.5 to 6.0 1.5 v ol 4 i ol =1ma 4.5 to 6.0 0.4 v ol 5 port 7, 8 i ol =0.5ma 2.5 to 6.0 0.4 v ol 6 i ol =8ma 4.5 to 6.0 1.5 low level output voltage v ol 7 port a, b, c, d, e, f i ol =1.4ma 2.5 to 6.0 0.4 vodls s0 to s47 i o =0ma vlcd, 2/3vlcd, 1/3vlcd level output refer to figure 8 2.5 to 6.0 0 0.2 lcd output voltage regulation vodlc com0 to com3 i o =0ma vlcd, 2/3vlcd, 1/2vlcd, 1/3vlcd level output refer to figure 8 2.5 to 6.0 0 0.2 v rlcd1 resistance per one bias resistor refer to figure 8 2.5 to 6.0 60 lcd bias resistor rlcd2 ?resistance per one bias resistor ?1/2r mode refer to figure 8 2.5 to 6.0 30 4.5 to 6.0 15 40 70 resistance of pull-up mos tr. rpu ?port 0, 1, 3, 7 ?port a, b, c, d, e, f v oh =0.9v dd 2.5 to 4.5 25 70 150 k ? vhis1 ?port 1, 7 ? res 2.5 to 6.0 0.1v dd hysterisis voltage vhis2 port 87 small signal input 2.5 to 6.0 0.1v dd v continued on next page.
lc8774c8b/b2b/96b/80b no.7773-13/22 continued from preceding page. parameter symbol pins conditions v dd [v] min typ max unit pin capacitance cp all pins ?all other terminals connected to v ss . ?f=1mhz ?ta=25 c 2.5 to 6.0 10 pf input sensitivity vsen port 87 small signal input 2.5 to 6.0 0.12v d d vp-p serial input / output characteristics / ta=-30 c to +70 c, v ss 1=v ss 2=v ss 3=0v parameter symbol pins conditions v dd [v] min typ max unit [serial clock] [input clock] cycle time tsck1 4/3 tsckl1 2/3 low level pulse width tsckla1 2/3 tsckh1 2/3 high level pulse width tsckha1 sck0(p12) refer to figure 6 2.5 to 6.0 5 cycle time tsck2 2 low level pulse width tsckl2 1 high level pulse width tsckh2 sck1(p15) refer to figure 6 2.5 to 6.0 1 tcyc [output clock] cycle time tsck3 4/3 tcyc tsckl3 1/2 low level pulse width tsckla2 3/4 tsckh3 1/2 high level pulse width tsckha2 sck0(p12) ?cmos output ?refer to figure 6 2.5 to 6.0 2 tsck cycle time tsck4 2 tcyc low level pulse width tsckl4 1/2 high level pulse width tsckh4 sck1(p15) ?cmos output ?refer to figure 6 2.5 to 6.0 1/2 tsck [serial input] 4.5 to 6.0 0.03 data set-up time tsdi 2.5 to 6.0 0.1 4.5 to 6.0 0.03 data hold time thdi si0(p11), si1(p14), sb0(p11), sb1(p14) ?measured with respect to sioclk leading edge ?refer to figure 6 2.5 to 6.0 0.1 s [serial output] 4.5 to 6.0 1/3tcy c +0.05 output delay time tddo so0(p10), so1(p13), sb0(p11), sb1(p14) ?when port is open drain: time delay from sioclk trailing edge to the so data change ?refer to figure 6 2.5 to 6.0 1/3tcy c +0.25 s
lc8774c8b/b2b/96b/80b no.7773-14/22 pulse input conditions / ta=-30 c to +70 c, v ss 1=v ss 2=v ss 3=0v parameter symbol pins conditions v dd [v] min typ max unit tpih1 tpil1 int0(p70), int1(p71), int2(p72), int4(p30 to p33), int5(p34 to p35) ?condition that interrupt is accepted ?condition that event input to timer 0 or 1 is accepted 2.5 to 6.0 1 tpih2 tpil2 int3(p73) (noise rejection ratio is 1/1.) ?condition that interrupt is accepted ?condition that event input to timer 0 is accepted 2.5 to 6.0 2 tpih3 tpil3 int3(p73) (noise rejection ratio is 1/32.) ?condition that interrupt is accepted ?condition that event input to timer 0 is accepted 2.5 to 6.0 64 tpih4 tpil4 int3(p73) (noise rejection ratio is 1/128.) ?condition that interrupt is accepted ?condition that event input to timer 0 is accepted 2.5 to 6.0 256 tpih5 tpil5 micin(p87) ?condition that signal is accepted to small signal detection counter 2.5 to 6.0 1 tcyc high / low level pulse width tpil6 res ?condition that reset is accepted 2.5 to 6.0 200 s ad converter characteristics / ta=-30 c to + 70 c, v ss 1=v ss 2=v ss 3=0v parameter symbol pins conditions v dd [v] min typ max unit resolution n 3.0 to 6.0 8 bit absolute precision et (note 2) 3.0 to 6.0 1.5 lsb 4.0 to 6.0 15.62 (tcyc= 0.488 s) 97.92 (tcyc= 3.06 s) ad conversion time = 32 tcyc (adcr2=0) (note 3) 3.0 to 6.0 23.52 (tcyc= 0.735 s) 97.92 (tcyc= 3.06 s) 4.5 to 6.0 18.82 (tcyc= 0.294 s) 97.92 (tcyc= 1.53 s) conversion time tcad ad conversion time = 64 tcyc (adcr2=1) (note 3) 3.0 to 6.0 47.04 (tcyc= 0.735 s) 97.92 (tcyc= 1.53 s) s analog input voltage range vain 3.0 to 6.0 v ss v dd v iainh vain=v dd 3.0 to 6.0 1 analog port input current iainl an0(p80) to an7(p87), an8(p70), an9(p71), an10(xt1), an11(xt2), an12(v1), an13(v2), an14(v3) vain=v ss 3.0 to 6.0 -1 a (note 2) absolute precision does not include quantizing error ( 1/2 lsb). (note 3) conversion time means time from executing ad conversion instruction to loading complete digital value to register.
lc8774c8b/b2b/96b/80b no.7773-15/22 current consumption characteristics / ta=-30 c to +70 c, v ss 1=v ss 2=v ss 3=0v parameter symbol pins conditions v dd [v] min typ max unit iddop1 ?fmcf=10mhz ceramic resonator oscillation ?fsx?tal=32.768khz crystal oscillation ?system clock: cf 10mhz oscillation ?internal rc oscillation stopped ?frequency variable rc oscillation stopped ?divider : 1/1 4.5 to 6.0 10.8 30 iddop2 ?cf1=20mhz external clock ?fsx?tal=32.768khz crystal oscillation ?system clock: cf1 oscillation ?internal rc oscillation stopped ?frequency variable rc oscillation stopped ?divider : 1/2 4.5 to 6.0 11.5 31 iddop3 4.5 to 6.0 5.1 17 iddop4 ?fmcf=4mhz ceramic resonator oscillation ?fsx?tal=32.768khz crystal oscillation ?system clock: cf 4mhz oscillation ?internal rc oscillation stopped ?frequency variable rc oscillation stopped ?divider : 1/1 2.5 to 4.5 2.6 11 iddop5 4.5 to 6.0 0.95 10 iddop6 ?fmcf=0hz (no oscillation) ?fsx?tal=32.768khz crystal oscillation ?frequency variable rc oscillation stopped ?system clock: rc oscillation ?divider : 1/2 2.5 to 4.5 0.45 6 iddop7 4.5 to 6.0 2.0 12 current consumption during normal operation (note 4) iddop8 v dd 1=v dd 2=v dd 3 ?fmcf=0hz (no oscillation) ?fsx?tal=32.768khz crystal oscillation ?internal rc oscillation stopped ?system clock: 1mhz with frequency variable rc oscillation ?divider : 1/2 2.5 to 4.5 1.6 8 ma continued on next page.
lc8774c8b/b2b/96b/80b no.7773-16/22 continued from preceding page. parameter symbol pins conditions v dd [v] min typ max unit iddop9 4.5 to 6.0 42 140 current consumption during normal operation (note 4) iddop10 v dd 1=v dd 2=v dd 3 ?fmcf=0hz (no oscillation) ?fsx?tal=32.768khz crystal oscillation ?system clock: 32.768khz ?internal rc oscillation stopped ?frequency variable rc oscillation stopped ?divider : 1/2 2.5 to 4.5 18 60 a iddhalt1 halt mode ?fmcf=10mhz ceramic resonator oscillation ?fsx?tal=32.768khz crystal oscillation ?system clock: cf 10mhz oscillation ?internal rc oscillation stopped ?frequency variable rc oscillation stopped ?divider : 1/1 4.5 to 6.0 3.7 12 iddhalt2 halt mode ?cf1=20mhz for external clock ?fsx?tal=32.768khz crystal oscillation ?system clock: cf1 oscillation ?internal rc oscillation stopped ?frequency variable rc oscillation stopped ?divider : 1/2 4.5 to 6.0 4.1 13 iddhalt3 4.5 to 6.0 1.8 6 iddhalt4 halt mode ?fmcf=4mhz ceramic resonator oscillation ?fsx?tal=32.768khz crystal oscillation ?system clock: cf 4mhz oscillation ?internal rc oscillation stopped ?frequency variable rc oscillation stopped ?divider : 1/1 2.5 to 4.5 1.0 5 ma iddhalt5 4.5 to 6.0 500 1600 current consumption during halt mode (note 4) iddhalt6 v dd 1=v dd 2=v dd 3 halt mode ?fmcf=0hz (oscillation stop) ?fsx?tal=32.768khz crystal oscillation ?internal rc oscillation stopped ?frequency variable rc oscillation stopped ?divider : 1/2 2.5 to 4.5 250 1300 a continued on next page.
lc8774c8b/b2b/96b/80b no.7773-17/22 continued from preceding page. parameter symbol pins conditions v dd [v] min typ max unit iddhalt7 4.5 to 6.0 1500 3600 iddhalt8 halt mode ?fmcf=0hz (no oscillation) ?fsx?tal=32.768khz crystal oscillation ?internal rc oscillation stopped ?system clock: 1mhz with frequency variable rc oscillation ?divider : 1/2 2.5 to 4.5 1250 3300 iddhalt9 4.5 to 6.0 25 100 current consumption during halt mode (note 4) iddhalt10 v dd 1=v dd 2=v dd 3 halt mode ?fmcf=0hz (oscillation stop) ?fsx?tal=32.768khz crystal oscillation ?system clock: 32.768khz ?internal rc oscillation stopped ? frequency variable rc oscillation stopped ?divider : 1/2 2.5 to 4.5 12 60 a iddhold1 4.5 to 6.0 0.05 25 current consumption during hold mode iddhold2 v dd 1 hold mode ?cf1=v dd or open (when using external clock) 2.5 to 4.5 0.015 20 iddhold3 4.5 to 6.0 20 90 current consumption during date / time clock hold mode iddhold4 v dd 1 date / time clock hold mode ?cf1=v dd or open (when using external clock) ?fmx?tal=32.768khz crystal oscillation 2.5 to 4.5 8 50 a (note 4) the currents through the output transistors and the pull-up mos transistors are ignored. main system clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: 1. use the standard evalua tion board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer. table 1. main system clock oscillation circuit characteristics using ceramic resonator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 [pf] c2 [pf] rd1 [ ? ] operating supply voltage range [v] typ [ms] max [ms] notes cstls10m0g53-b0 (15) (15) 220 4.5 to 6.0 0.05 0.25 built-in c1, c2 10mhz murata cstce10m0g52-r0 (10) (10) 220 4.5 to 6.0 0.05 0.25 built-in c1, c2 cstls4m00g53-b0 (15) (15) 470 2.5 to 6.0 0.05 0.25 built-in c1, c2 4mhz murata cstcr4m00g53-r0 (15) (15) 1k 2.5 to 6.0 0.06 0.3 built-in c1, c2 the oscillation stabilizing time is a period until the oscillation becomes stable after v dd becomes higher than minimum operating voltage. (refer to figure 4)
lc8774c8b/b2b/96b/80b no.7773-18/22 subsystem clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: 1. use the standard evalua tion board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer. table 2. subsystem clock oscillation circuit characteristics using crystal oscillator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c3 [pf] c4 [pf] rf [ ? ] rd2 [k ? ] operating supply voltage range [v] typ [s] max [s] notes 32.768khz seiko epson mc-306 18 18 open 390 2.5 to 6.0 1.1 3.0 applicable cl value = 12.5pf the oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the hold mode. (refer to figure 4) (notes) ? since the circuit pattern affects the oscillation fre quency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit figure 3 ac timing measurement point 0.5v dd c3 rd2 c4 x?tal xt2 xt1 rf c1 c2 cf cf2 cf1 rd1
lc8774c8b/b2b/96b/80b no.7773-19/22 reset time and oscillation stable time hold release signal and oscillation stable time figure 4 oscillation stabilizing time internal rc oscillation cf1 , cf2 xt1 , xt2 operation mode hold release signal without hold release signal hold release signal valid tmscf tmsxtal hold halt power supply res internal rc oscillation cf1, cf2 xt1 , xt2 o perat i on mo d e reset time tmscf tmsxtal unfixed reset instruction execution mode v dd v dd limit 0v
lc8774c8b/b2b/96b/80b no.7773-20/22 figure 5 reset circuit figure 6 serial input / output wave form (note) select c res and r res value to assure that at least 200s reset time is generated after the v dd becomes higher than the minimum operating voltage. c res v dd r res res sioclk datain dataout di0 di1 di2 di3 di4 di5 di6 di7 di8 do0 do1 do2 do3 do4 do5 do6 do7 do8 data ram transmission period (only sio0) sioclk datain dataout tsck tsckl tsckh tsdi thdi tddo sioclk datain dataout tddo tsdi thdi tsckla tsckha data ram transmission period (only sio0)
lc8774c8b/b2b/96b/80b no.7773-21/22 figure 7 pulse input timing figure 8 lcd bias resistor tpil tpih vlcd sw : on (vlcd=v dd ) 2/3vlcd 1/2vlcd 1/3vlcd sw : on / off (programmable) v dd gnd rlcd rlcd rlcd rlcd rlcd rlcd rlcd rlcd rlcd rlcd
lc8774c8b/b2b/96b/80b no.7773-22/22 ps

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